Reconfigurable memory with selectable error correction storage

ABSTRACT

A memory structure includes a memory module divided into low order banks and high order banks. The low order banks are used as conventional memory. The high order banks are used as either conventional memory or ECC memory, depending upon routing of data. In one embodiment, data from the high order banks are routed through a primary multiplexer to a data bus when the high order banks are used as conventional memory. When the high order banks are used as ECC memory, data from the auxiliary section is routed through the primary multiplexer to an error correction circuit. A secondary multiplexer combines ECC bits from the auxiliary section of the module or a dedicated ECC memory on a motherboard. The auxiliary section thus supplements the onboard ECC memory to provide support for an effectively larger ECC memory for use with error intolerant applications that require error correction.

TECHNICAL FIELD

[0001] The present invention relates to memory structures for computers,and more particularly, to error correction in computer memories.

BACKGROUND OF THE INVENTION

[0002] Semiconductor memory systems are subject to errors. That is, dataretrieved from the memory does not always match data that was originallywritten to the memory. Such errors can be caused by stray alphaparticles, damage to the memory devices or by a variety of operatingconditions, such as power supply fluctuations, noise, etc. Regardless ofthe source, such errors are clearly undesirable. Consequently, mostmodern memory systems include error detection and/or error correctioncapabilities.

[0003] Typical approaches to detecting and correcting errors in memoryrely upon some form of error correction code to identify and correctsuch data errors. Such error correction codes typically include amathematical algorithm that is applied to the data to be checked andcorrected, and additional error correction code (“ECC”) bits. Usually,the ECC bits are stored in a separate memory dedicated to the ECC bits.The amount of memory dedicated to storing the ECC bits can besignificant. For example, the memory overhead for the ECC bits can oftenexceed 10%.

[0004] The amount of ECC bits required can depend upon the type of errorcorrection code being utilized. In some applications, very little or noerror correction is desired. For example, in video games, occasionalimage data errors are unlikely to significantly affect the imagesperceived by a user. Rather than devote processor power to errorcorrection calculations and memory to ECC bits, such applicationslargely ignore image data errors to increase the speed of play. Suchapplications will be referred to herein as error tolerant applications.Error tolerant applications typically use no error correctioncalculations or limited error correction algorithms that require littleor no ECC memory.

[0005] Other applications can tolerate little or no data errors. Forexample, data errors can be extremely undesirable in accountingprograms. Such applications will be referred to herein as errorintolerant applications. Error intolerant applications usually utilizerobust error correction algorithms requiring a substantial amount of ECCmemory.

[0006] Typically, memory devices for storing ECC bits are segregatedfrom memory devices for conventional data. For example, 144 pin 4-MB×64double in-line memory module (“DIMM”) not used to store ECC bits couldbe implemented using 16 4-MB×4 dynamic random access memories (“DRAMs”).However, the same data storage capacity plus the capacity to store ECCbits would require a 4-MB×72 DIMM implemented using 18 4-MB×4 DRAMs.Thus, implementing ECC requires two additional DRAMs.

[0007] One problem with such memory architectures is that they do notfully utilize the available memory capacity. For example, error tolerantapplications do not need nor use the extra memory provided to store ECCbits. Thus, valuable memory capacity is left unused. In the aboveexample, 11% of the DRAMs on the DIMM are wasted when the DIMM is notused to store ECC bits

[0008] On the other hand, error intolerant applications require morememory and are often limited by the amount of available ECC memory.Consequently, the speed with which the application runs can be increasedby increasing the amount of available ECC memory. Adding such memory canbe costly. Moreover, adding such memory capacity increases the amount ofunused memory in error tolerant applications.

SUMMARY OF THE INVENTION

[0009] A software or hardware controlled reconfigurable memory systemincludes an auxiliary section of one or more data banks that can beselectively utilized as conventional memory or ECC memory, dependingupon the particular application. In one embodiment, the auxiliarysection is part of a memory module that includes a primary sectiondirectly coupled to an output data bus for conventional memory uses. Aprimary multiplexer selectively couples the auxiliary section to eitherthe output data bus or to an error checking circuit, depending upon theselected configuration of the system. If the system runs an errorintolerant application employing a robust error correction algorithm,the auxiliary section is coupled to the error correction circuit tostore ECC data for ECC calculations. In error tolerant applications notrequiring error correction, the auxiliary section is coupled to theoutput data bus to supplement the conventional memory, thereby providingincreased memory capacity and improving speed of the system.

[0010] One embodiment of the invention also includes a dedicated ECCmemory, which could be located on the motherboard. A secondarymultiplexer receives data from the dedicated ECC memory at one input anddata from the primary multiplexer at a second input. The primary andsecondary multiplexers are controlled by software or hardware toestablish the amount of ECC memory being used. For error intolerantapplications, the primary multiplexer is activated to couple data fromthe auxiliary section to one input of the secondary multiplexer. Thesecondary multiplexer is then activated to couple data from both theprimary multiplexer and the dedicated ECC memory to the error correctioncircuit. Thus, the auxiliary section is used to supplement the dedicatedECC memory in error intolerant applications where additional ECC memoryis desirable.

[0011] In one embodiment, the second input of the secondary multiplexeris coupled to a set of memory sockets on the motherboard. The secondarymultiplexer selectively couples only those sockets containing memorychips to the error correction circuit. Also, the primary and secondarymultiplexers are controlled to select an appropriate portion of theauxiliary section to supplement the dedicated ECC memory, according tothe ECC data requirements of an application and the amount of availablededicated ECC memory.

[0012] In one embodiment, the auxiliary section is segmented into twosections. The first section is used to supplement the dedicated ECCmemory from the motherboard. The second section is used as a supplementto the conventional memory. To accommodate the difference in word lengthcaused by segmenting of the auxiliary section, the second section is“double-written” and “double-read” so that data is written to and readfrom the second section in two or more pieces. When reading the data,the two or more pieces are combined to form the complete written data.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block diagram of a memory system according to anembodiment of the invention on which a memory device is selectivelycoupled to either an output data bus or to an error correction circuitby a primary multiplexer.

[0014]FIG. 2 is a more detailed block diagram of the memory system ofFIG. 1 coupled to a memory controller.

[0015]FIG. 3 is a block diagram of another embodiment of the memorysystem of FIG. 1.

[0016]FIG. 4 is a block diagram of still another embodiment of thememory system of FIG. 1.

[0017]FIG. 5 is a block diagram of a computer system according to oneembodiment of the invention including input and output devices, aprocessor, and the memory system of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

[0018] As shown in FIG. 1, a memory system 40 according to an embodimentof the invention includes as its central storage element a memory array42 having at least one low-order bank 44 and at least one high-orderbank 46. The memory array 42 is formed from one or more integratedmemory devices. The devices may be any suitable type of memory device,such as dynamic random access memories (DRAMs), static RAMs (SRAMs), ornon-volatile memory devices. The memory devices may also be synchronousor asynchronous, or some other variety of memory device.

[0019] Data that are to be written to and read from the memory array 42are coupled to and from the array 42 along a 64-bit primary data path 48and a 64-bit auxiliary data path 50, respectively. The primary data path48 extends directly from the low order banks 44 to a data bus 52.Although the embodiment of FIG. 1 uses 64-bit buses 48, 50, it will bebetter understood that higher or lower capacity buses may be used.

[0020] The auxiliary data path 50 is coupled to a primary multiplexer54, which is a 64-bit, 1-to-2 multiplexer. In response to a mode selectinput MODE, the primary multiplexer 54 selectively couples data from thehigh order banks 46 to either the data bus 52 or to an error correctioncircuit 56. The high order banks 46 can therefore provide storage forECC bits or can provide storage to supplement the primary section 44.

[0021]FIG. 2 shows the memory system 40 of FIG. 1 in greater detail inconjunction with a separate error correction memory (ECC memory) 58. Inthis embodiment, the memory array 42 includes eight memory banks 60 ₀-60₇ where the first seven banks 60 ₀-60 ₆ correspond to the low orderbanks of FIG. 1 and the eighth memory bank 60 ₇ corresponds to the highorder bank 46 of FIG. 1. The output of the eighth bank 60 ₇ is input tothe primary multiplexer 54 through the auxiliary data path 50 while theoutputs of the first seven banks 60 ₀-60 ₆ are connected directly to thedata bus 52.

[0022] Switching of the primary multiplexer 54 is controlled by a memorycontroller 63 through a mode signal MODE, in response to either softwareor hardware commands. Depending upon the state of the mode signal MODE,the primary multiplexer 54 couples data from the eighth data bank 60 ₇to either the data bus 52 or to a secondary multiplexer 64. If the modesignal MODE is high, the primary multiplexer 54 directs data to the databus 52. If the mode signal MODE is low, the primary multiplexer 54directs data to the secondary multiplexer 64.

[0023] Like the primary multiplexer 54, the secondary multiplexer 64includes eight, 8-bit 2-to-1 multiplexers, rather than eight, 8-bit1-to-2 multiplexers. Thus, the 64 outputs of the primary multiplexer 54are coupled to a first set of 64 inputs of the secondary multiplexer 64.The second set of 64 inputs of the secondary multiplexer 64 is coupledto the ECC memory 58. When enabled by the mode signal MODE and by anerror correction enable signal ECCENABLE, the secondary multiplexer 64couples one of eight 8-bit bytes of ECC data to the error correctioncircuit 56 as determined by a SELECT input from the memory controller.The first two 8-bit bytes of ECC data are supplied by respective ECCchips 68 in the ECC memory 58. The remaining six 8-bit bytes aresupplied by the high order banks 46 through the primary multiplexer 54.

[0024] The error correction circuit 56 operates on the 8 bits of ECCdata ECC₀-ECC₇ to identify and correct errors according to conventionalerror correction techniques, such as Hamming code or similar correctionalgorithms. The error correction circuit 56 may be implemented asdedicated hardware or as a software program in a processor 210 (FIG. 5).

[0025] In operation, the memory system 40 can operate in either an errortolerant mode or an error intolerant mode. In the error tolerant mode,the primary multiplexer 54 couples the high order bank 60 ₇ to the databus 52 so that all 8 banks 60 ₀-60₇ are used for storing data. In theerror intolerant mode, the primary multiplexer 54 couples the high orderbank 60 ₇ to the secondary multiplexer 64, the secondary multiplexer 64then couples the high order bank 60 ₇ to the error correction circuit56. Alternatively, the secondary multiplexer 64 can couple the ECCmemory 68 to the error correction circuit 56. In either case, when dataare written to the low order banks 60 ₀-60 ₆, 8 ECC check bits areapplied to the error correction circuit 56. The error correction circuit56 then couples 64 bits to the high order banks 60 ₇ through thesecondary multiplexer 64 and the primary multiplexer 54.

[0026] During a read operation, data are coupled from the low orderbanks 60 ₀-60 ₆ to the data bus 52, and corresponding ECC data arecoupled from the high order bank 60 ₇ through the multiplexer 54, 64 tothe error correction circuit 56. The error correction circuit 56 thenchecks the 8 ECC bits in a conventional manner to detect and correcterrors in the data coupled to the data bus 52.

[0027]FIG. 3 shows the system of FIG. 2 where the error correctionimplementation is less robust, i.e., ECC data is supplied only by theECC memory 58 on the mother board. Consequently, the two ECC chips 68 inthe ECC memory 58 provide the ECC data for banks 60 ₀ and 60 ₁ only. Thesecondary multiplexer 64 thus outputs only the ECC data for the banks 60₀ and 60 ₁ to the error correction circuit 56. More memory chips wouldneed to be added to ECC memory 58 in order to support more databanks 60₂-60 ₆.

[0028]FIG. 4 shows another embodiment of the invention in which the ECCmemory 58 includes four ECC chips 68 and which uses an error correctionalgorithm involving 8-bits of ECC data ECC₀-ECC₇. The four ECC chips 68supply the ECC data for banks 60 ₀-60₃. Therefore, only half of the highorder bank 60 ₇ is used for error correction of banks 60 ₄-60₇,leavinghalf of the high order bank 60 ₇ free for conventional memory use.Instead of leaving half of the high order bank 60 ₇ unused, the highorder bank 60 ₇ is broken into two subsections 46A, 46B where the firstsubsection 46A contains ECC data and the second subsection 46B is usedas conventional memory to supplement the low order banks 60 ₀-60 ₆. Thefirst subsection 46A provides the second four 8-bit bytes of errorcorrection data used for memory bank 60 ₀-60 ₃ to the secondarymultiplexer 64 through the primary multiplexer 54 in a similar fashionto that described above for FIG. 2. The secondary multiplexer 64 selectseither the on-board ECC data for banks 60 ₄-60 ₇ or the auxiliary ECCdata for banks 60 ₀-60 ₃.

[0029] The second subsection 46B of the high order bank 60 ₇ is notwasted. Instead, the second subsection 46B provides data to the data bus52 through the primary multiplexer 54. One skilled in the art willrecognize that the second subsection 46B will only be comprised of amemory bank that is half the depth of the banks 60 ₀-60 ₆. Since thehigh order bank 60 ₇ cannot both supply data and ECC bitssimultaneously, the on board ECC memory 58 must supply the ECC data forthe second subsection of the high order bank 60 ₇.

[0030]FIG. 5 is a block diagram of a computer system 200 that uses oneof the embodiments of FIG. 2-4. The computer system 200 includes aprocessor 210 for performing computer functions, such as executingsoftware to perform desired calculations and tasks. The processor 210accesses the memory module 40 and ECC memory 58 through the data bus 52by activating the memory controller 63 which, in turn, controls themultiplexers 54, 64. The memory module 40 and the ECC memory 58 arepreferably mounted at separate locations within the computer system 200with the ECC memory 58 being mounted to a common board with theprocessor 210. The memory module 40 and ECC memory 58 are coupled to theprocessor 210 through the date bus 52. The processor 210 is also coupledto the error correction circuit 56 to receive error detection andcorrection information that the processor 210 uses to control the memorycontroller 63. One or more input devices 214, such as a keypad or amouse, are coupled to the processor 210 through an I/O controller 216and allow an operator (not shown) to manually input data thereto. One ormore output devices 218 are coupled to the processor 210 through the I/Ocontroller to provide to the operator data generated by the processor210 or retrieved from the memory module 40. Examples of output devices218 include a printer and a video display unit. One or more mass datastorage devices 220 are preferably coupled to the processor 210 throughthe I/O controller 216 to store data in or retrieve data from thestorage device 220. Examples of the storage devices 220 include diskdrives and compact disk read-only memories (CD-ROMs).

[0031] While the present invention has been described herein by way ofexemplary embodiments, various modifications may be made withoutdeparting from the scope of the invention. For example, the number ofECC chips 68 in the ECC memory 58 may be larger or smaller. Also, thesecondary multiplexer 64 can be configured to vary the multiplexing ofthe ECC data in response to the enable signal ECC ENABLE, so that thecombination of bits from the ECC memory 58 and auxiliary section 46 canbe controlled remotely by the memory controller 63. Additionally, thehigh order bank 46 may include more than one bank of the memory array42. Further, the memory array 42 may include fewer or more than eightbanks. And, the ECC memory 58 can be located off the motherboard in someapplications. Moreover, the error correction circuit 56 and/or thememory controller 63 can be implemented in whole or in part by theprocessor 210 in response to software. Also, the number of bits in eachbank or on the data busses may be fewer than or more than the 64-bit busstructure described herein. Accordingly, the invention is not limitedexcept as by the appended claims. Exhibit A Appl. No. Atty Dkt #Applicants Filed Title 09/359,926 500420.01 Brett Williams and 22 Jul.1999 Reconfigurable Memory With Selectable (660073.658) Don BaldwinError Correction Storage Not yet 500420.03 Brett Williams and 10 Aug.2001 Reconfigurable Memory With Selectable assigned Don Baldwin ErrorCorrection Storage

1. A memory control circuit for a computer system, comprising: a memorysystem having a plurality of memory locations corresponding torespective addresses; an error correction circuit; a data bus coupled toa first set of memory locations of the memory system; and a couplingdevice coupling a second set of memory locations of the memory system tothe error correction circuit.
 2. The memory control circuit of claim 1wherein the coupling device comprises a first switching circuit having afirst data port coupled to the second set of memory locations of thememory system, a second data port coupled to the data bus, a third dataport coupled to the error correction circuit, and a mode select input,the switching circuit being operable responsive to a first mode selectsignal to couple the first data port to the second data port, and beingoperable responsive to a second mode select signal to couple the firstdata port to the third data port.
 3. The memory control circuit of claim2 further comprising an error correction memory, and wherein thecoupling circuit further comprises a second switching circuit having afirst data port coupled to the third data port of the first switchingcircuit, a second data port coupled to the error correction memory, athird data port coupled to the error correction circuit, and a controlinput, the second switching circuit being operable responsive to a firstcontrol signal to couple the first data port to the third data port, andbeing operable responsive to a second control signal to couple thesecond data port to the third data port.
 4. The memory control circuitof claim 3 wherein the data ports of the first switching circuitcomprise a first plurality of sets of data lines, and the second dataport of the second switching circuit comprises a second plurality ofsets of data lines, the second switching circuit being operableresponsive to the first control signal to couple one of the sets in thefirst plurality of sets of data lines to the error correction circuit,and being operable responsive to the second control signal to couple oneof the sets in the second plurality of sets of data lines to the errorcorrection circuit.
 5. The memory control circuit of claim 2 furthercomprising an error correction memory, and wherein the switching circuitcomprises: a first multiplexer having a first data port coupled to thesecond set of locations of the memory system, a second data port coupledto the data bus, a third data port, and a control input, the firstmultiplexer being operable responsive to a first control signal appliedto the control input to couple the first data port to the second dataport, and being operable responsive to a second control signal to couplethe first data port to the third data port; and a second multiplexerhaving a first data port coupled to the third data port of the firstmultiplexer, a second data port coupled to the error correction memory,a third data port coupled to the error correction circuit, and a controlinput, the second multiplexer being operable responsive to a thirdcontrol signal applied to the control input to couple the first dataport to the third data port, and being operable responsive to a fourthcontrol signal to couple the second data port to the third data port. 6.The memory control circuit of claim 1 wherein the memory systemcomprises a memory device having a plurality of banks.
 7. The memorycontrol circuit of claim 6 wherein the first set of memory locations ofthe memory system comprise a first set of banks of the memory device,and the second set of memory locations of the memory system comprise asecond set of banks of the memory device.
 8. The memory control circuitof claim 7 wherein the second set of banks comprises a single bank. 9.The memory control circuit of claim 7 wherein the second set of bankscomprise a first set of memory locations coupled to the data bus, and asecond set of memory locations coupled to the error correction circuit.10. The memory control circuit of claim 1 wherein the memory systemcomprises: a first memory device having a plurality of banks, a firstset of banks of the first memory device being coupled to the data bus;and a set of second memory devices.
 11. The memory control circuit ofclaim 10 wherein the coupling device comprises a switching circuithaving a plurality of first data ports coupled to respective secondmemory devices in the set of second memory devices, a second data portcoupled to the error correction circuit, and a control input, theswitching circuit being operable responsive to a control signal appliedto the control input to couple one of the first data ports to the seconddata port responsive to a corresponding control signal.
 12. An memorysystem operable in either normal mode or an error correcting mode,comprising: a memory device having a plurality of banks; a data buscoupled to a first set of banks of the memory device; an errorcorrection circuit; a first switching circuit having a first portcoupled to at least one bank of the memory device, a second port coupledto the data bus, a third port coupled to the error correction circuit,and a mode input coupled to receive a mode signal having a first stateindicative of the normal mode and a second state indicative of the errorcorrecting mode, the first switching circuit being structured to couplethe first port to the second port responsive to a mode signal having thefirst state and to couple the first port to the third port responsive toa mode signal having the second state.
 13. The memory system of claim 12wherein the bank of the memory device to which the first port of thefirst switching circuit is coupled comprises a bank of the memory deviceother than an bank in the first set.
 14. The memory system of claim 12wherein the bank of the memory device to which the first port of thefirst switching circuit is coupled comprises one of the banks in thefirst set of banks of the memory device, a first plurality of memorylocations in the bank being coupled to the data bus and a secondplurality of memory locations in the bank being coupled to the firstport of the first switching circuit.
 15. An memory system operable ineither normal mode or an error correcting mode, comprising: a firstmemory device having a plurality of banks; a second memory device; adata bus coupled to a first set of banks of the first memory device; anerror correction circuit; a first switching circuit having a first portcoupled to at least one bank of the first memory device, a second portcoupled to the data bus, a third port, and a mode input coupled toreceive a mode signal having a first state indicative of the normal modeand a second state indicative of the error correcting mode, the firstswitching circuit being structured to couple the first port to thesecond port responsive to a mode signal having the first state and tocouple the first port to the third port responsive to a mode signalhaving the second state; and a second switching circuit having a firstplurality of signal terminal sets coupled to the third port of the firstswitching circuit, a second plurality of signal terminal sets coupled tothe second memory device, a set of signal terminals coupled to the errorcorrection circuit, and a select input coupled to receive a selectsignal, the second switching circuit being structured to couple the oneof the signal terminal sets in the first plurality or one of the signalterminal sets in the second plurality to the error correction circuitresponsive to the select signal.
 16. The memory system of claim 15wherein the bank of the memory device to which the first port of thefirst switching circuit is coupled comprises a bank of the memory deviceother than an bank in the first set.
 17. The memory system of claim 15wherein the bank of the memory device to which the first port of thefirst switching circuit is coupled comprises one of the banks in thefirst set of banks of the memory device, a first plurality of memorylocations in the bank being coupled to the data bus and a secondplurality of memory locations in the bank being coupled to the firstport of the first switching circuit.
 18. A computer system, comprising:a processor; a data bus; a peripheral device coupled to the processor; amemory system having a plurality of memory locations, a first set of thememory locations being coupled to the data bus; an error correctioncircuit; a coupling device coupling a second set of memory locations ofthe memory system to the error correction circuit.
 19. The computersystem of claim 18, wherein the memory correction circuit includes amemory correction port, and wherein the processor is coupled to thememory correction port and to the data bus, the processor beingstructured to couple data to or from the data bus and a correspondingerror correction code to or from the memory correction port,respectively.
 20. The computer system of claim 18 wherein the couplingdevice comprises a first switching circuit having a first data portcoupled to the second set of memory locations of the memory system, asecond data port coupled to the data bus, a third data port coupled tothe error correction circuit, and a mode select input, the switchingcircuit being operable responsive to a first mode select signal tocouple the first data port to the second data port, and being operableresponsive to a second mode select signal to couple the first data portto the third data port.
 21. The computer system of claim 19 furthercomprising an error correction memory, and wherein the coupling circuitfurther comprises a second switching circuit having a first data portcoupled to the third data port of the first switching circuit, a seconddata port coupled to the error correction memory, a third data portcoupled to the error correction circuit, and a control input, the secondswitching circuit being operable responsive to a first control signal tocouple the first data port to the third data port, and being operableresponsive to a second control signal to couple the second data port tothe third data port.
 22. The computer system of claim 21 wherein thedata ports of the first switching circuit comprise a first plurality ofsets of data lines, and the second data port of the second switchingcircuit comprises a second plurality of sets of data lines, the secondswitching circuit being operable responsive to the first control signalto couple one of the sets in the first plurality of sets of data linesto the error correction circuit, and being operable responsive to thesecond control signal to couple one of the sets in the second pluralityof sets of data lines to the error correction circuit.
 23. The computersystem of claim 20 further comprising an error correction memory, andwherein the switching circuit comprises: a first multiplexer having afirst data port coupled to the second set of locations of the memorysystem, a second data port coupled to the data bus, a third data port,and a control input, the first multiplexer being operable responsive toa first control signal applied to the control input to couple the firstdata port to the second data port, and being operable responsive to asecond control signal to couple the first data port to the third dataport; and a second multiplexer having a first data port coupled to thethird data port of the first multiplexer, a second data port coupled tothe error correction memory, a third data port coupled to the errorcorrection circuit, and a control input, the second multiplexer beingoperable responsive to a third control signal applied to the controlinput to couple the first data port to the third data port, and beingoperable responsive to a fourth control signal to couple the second dataport to the third data port.
 24. The computer system of claim 18 whereinthe memory system comprises a memory device having a plurality of banks.25. The computer system of claim 24 wherein the first set of memorylocations of the memory system comprise a first set of banks of thememory device, and the second set of memory locations of the memorysystem comprise a second set of banks of the memory device.
 26. Thecomputer system of claim 25 wherein the second set of banks comprises asingle bank. 27.The computer system of claim 25 wherein the second setof banks comprise a first set of memory locations coupled to the databus, and a second set of memory locations coupled to the errorcorrection circuit.
 28. The computer system of claim 18 wherein thememory system comprises: a first memory device having a plurality ofbanks, a first set of banks of the first memory device being coupled tothe data bus; and a set of second memory devices.
 29. The computersystem of claim 28 wherein the coupling device comprises a switchingcircuit having a plurality of first data ports coupled to respectivesecond memory devices in the set of second memory devices, a second dataport coupled to the error correction circuit, and a control input, theswitching circuit being operable responsive to a control signal appliedto the control input to couple one of the first data ports to the seconddata port responsive to a corresponding control signal.
 30. A method ofstoring and retrieving data in a memory system operable in either anerror tolerant mode or an error intolerant mode, the method comprising:coupling a first plurality of locations of the memory system to a databus so that data applied to the data bus can be written to the firstplurality of locations of the memory system and data read from the firstplurality of locations of the memory system can be applied to the databus; coupling a second plurality of locations of the memory system tothe data bus when the memory system is operating in the error tolerantmode; and coupling the second plurality of locations of the memorysystem to an error correction circuit when the memory system isoperating in the error intolerant mode.
 31. The method of claim 30wherein the first and second plurality of locations of the memory systemcomprise different banks of a single memory device.
 32. The method ofclaim 30 wherein the first and second plurality of locations of thememory system comprise different memory devices.
 33. The method of claim30, further comprising: applying data to the data bus when the memorysystem is operating in the error intolerant mode; applying acorresponding error correction code to the error correction circuit, theerror correction code coupling corresponding error correction bits tothe second plurality of locations of the memory system; writing the datain at least some of the memory locations in the first plurality oflocations of the memory system; writing the error correction bits in atleast some of the memory locations in the second plurality of locationsof the memory system; reading data from at least some of the memorylocations in the first plurality of locations of the memory system;reading error correction bits from at least some of the memory locationsin the second plurality of locations of the memory system, the readerror correction bits corresponding to the data read from the memorylocations in the first plurality; determining from the error correctionbits if the read data is in error; and if the read data is determined tobe in error, correcting the read data.
 34. A method of storing data in amemory device having first and second memory portions, comprising:selecting either an error correction mode or a non-error correctionmode; storing data in the first memory portion; if the error correctionmode is selected, storing error correction bits corresponding to thedata in the second memory portion; and if the non-error correction modeis selected, storing information data in the second memory portion. 35.The method of claim 34 further comprising: retrieving data from thefirst memory portion; if the error correction mode is selected,retrieving error correction bits corresponding to the data from thesecond memory portion; and if the non-error correction mode is selected,retrieving data from the second memory portion.
 36. The method of claim35 further comprising, if the error correction mode is selected:determining from the error correction bits if the retrieved data is inerror; and if the retrieved data is determined to be in error,correcting the retrieved data using the error correction bits.
 37. Themethod of claim 34 wherein the storing of data in the second memoryportion comprises: storing a first segment of a data byte in a firstlocation having a first address in the second memory portion; andstoring a second segment of the data byte in a second location having asecond address in the second memory portion.
 38. The method of claim 37,further comprising: retrieving the stored first segment from the firstlocation at a first time; retrieving the stored second segment from thesecond location at a second time different from the first time; andcombining the retrieved first and second segments.
 39. A method ofretrieving data from a memory device having first and second memoryportions, comprising: selecting either an error correction mode or anon-error correction mode; retrieving data from the first memoryportion; if the error correction mode is selected, retrieving errorcorrection bits corresponding to the data from the second memoryportion; and if the non-error correction mode is selected, retrievingdata from the second memory portion.
 40. The method of claim 39 furthercomprising, if the error correction mode is selected: determining fromthe error correction bits if the retrieved data is in error; and if theretrieved data is determined to be in error, correcting the retrieveddata using the error correction bits.